1. Field of the Invention
The present invention relates to a multi-chip semiconductor device which comprises two or more semiconductor chips, and a plurality of inter-chip wires for transferring data in synchronization with a clock signal between the semiconductor chips, and more particularly, to a method of transferring data between the chips.
2. Description of the Related Art
Miniaturization of semiconductor integrated circuits has improved the density of integration, and promotes higher performance of CPU and larger memory capacities. However, since miniaturization of semiconductor integrated circuits has limitations, the introduction of new technologies has been needed for further increasing the density of integration. As one such technology, there is a semiconductor device, called a system-in-package or a multi-chip package, which comprises a multi-chip having laminated semiconductor chips within a package. In these semiconductor devices, although chips are interconnected through bonding wires, the number of wires is limited to approximately one hundred. Thus, in order to further increase the number of wires between chips, a through-wire has been proposed to increase the wiring density by passing wires through semiconductor substrates of chips from the front surface to the back surface. K. Takahashi et al., Japanese Journal of Applied Physics, 40, 3032 (2001) has proposed to reduce the thickness of an Si substrate of a semiconductor chip to 50 μm, piercing a hole of 10 μm square extending through the substrate from the front surface to the back surface, and filling the hole with a metal to form a through wire for inter-chip wiring. This through wiring enables inter-chip wires to be routed on the surface of a chip two-dimensionally to accomplish even several thousands of inter-chip wires.
If the number of inter-chip wires increases to several thousands due to through wiring, even 1% of faulty through wires means that there will be essentially no good lamination type semiconductor devices. Thus, spare inter-chip wires are provided for purposes of redundancy, and are used to transfer data to be transferred through a faulty inter-chip so that the total amount of data to be transferred between chips is not reduced. However, if the number of faulty inter-chip wires increases by several tens of percent, the total number of inter-chip wires also increases by several tens of percent due to the spare inter-chip wires. For example, if there are 5,000 inter-chip wires and the percent defective is 10%, then at least 500 spare inter-chip wires are required. This results in an area overhead of 1.25 mm2 in a chip surface if the inter-chip wiring employs through wires with a wiring pitch of 50 μm. In spite of a semiconductor device being multi-layered to increase the density of semiconductor circuits, the area occupied by the spare inter-chip wires can limit improvement in the density of semiconductor circuits.
JP2002-334600A discloses a semiconductor integrated circuit wherein two groups of semiconductor integrated circuits are provided and when one bus group fails, outputs from a non-volatile memory are switched to the other bus group. JP2004-118987A discloses conducting diagnosis on memory cells in a semiconductor integrated circuit device as to which memory cell(s) is/are faulty. It is to be noted that in any of the inventions described in these patent documents, the target of the test is not inter-chip wires.